moduleShiftReg(clk，rst，l_in，s，q);inputclk，rst，l_in，s;output[]q;reg[]q;//在always语句中被赋值的信号要声明为reg类型always@(posedgeclk)beginif(rst)q<=’b;elseif(s)q<={q[]，l_in};elseq<=q;endendmodule